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Chapter 5: VSK Diagnostics and Support Tool Kit
R
Bitstream
The VIO block can be used in a design that is targeted for being generated as a bitstream
directly from System Generator. Figure 5-9 is an example of a standalone bitstream design.
In this design, the VIO receives video from the VIODC and provides that data on its vout
port to the VOP block for processing. The output of the VOP block is routed around to the
vin input of the VIO block. The VIO then routes that data up to the VIODC for display.
Figure 5-9: VIO Bitstream Design
The user can use the VIO mask to select the input and output types that the design will
initialize at start-up. The user is responsible for making sure that the Compile Type is set to
Bitstream before the design bitstream is generated.
There are input and output gateways in the VIO that must be connected to the proper
FPGA pins. To designate those pin locations, there is a .ucf file that must accompany a
bitstream design that uses the VIO block. An example of this .ucf file can be found on the
VSK CDROM at Examples\VSK_StandAlone . The file is called DesignName_cw.ucf .
This file must be copied into the target directory that the user specifies for building the
bitstream. The file should be renamed to <design_name>_cw.ucf . (e.g.,
vsk_vio_vio_cw.ucf )
There are two ways to accomplish this:
1.
2.
Create the directory structure and copy the .ucf file into the target directory before
generating the bitstream.
Generate the bitstream, copy the .ucf file into the created target directory, and
regenerate the bitstream. If the .ucf file is not present in the target directory when the
bitstream is created, the bitstream is generated, but the FPGA pins are selected
78
www.xilinx.com
Video Starter Kit
UG217 (v1.5) October 26, 2006
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